The present invention relates to a memory device. More particularly, the present invention relates to a semiconductor device having a surrounded channel transistor and a method for fabricating the same.
When the channel length of a cell transistor is decreased, the ion concentration of the cell channel structure is generally increased in order to maintain threshold voltage of the cell transistor. Due to the increase in the ion concentration of the cell channel structure, an electric field in the source/drain regions of the cell transistor is enhanced to increase leakage current. This results in the degradation of the refresh characteristics of a DRAM structure. In addition, as the semiconductor device shrinks to smaller sizes, it is difficult to effectively control the short channel effect (“SCE”). Therefore, Multi-channel Field Effect Transistors (“McFET”) such as a recessed channel transistor and a fin channel transistor have been proposed to increase the channel length of the cell transistor.
However, the degree of process complexity is increased due to the additional deposition process and planarization process in the McFET technology. As the design rules of the device become smaller, it is difficult to control the height and width of the fin channel transistor. Because the bottom of the fin channel transistor is connected to the semiconductor substrate, punch-through between source/drain regions easily occurs when the height of the fin channel transistor is less than the depth of the source/drain regions according to shrinkage of the design rules. Accordingly, there is a need for a new structure of the transistor in order to improve the performance of the device.